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1. general description the P89LPC9301/931a1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system-level functions have been incorporated into the P89LPC9301/931a1 in order to reduce component count, board space, and system cost. 2. features 2.1 principal features n 4 kb/8 kb byte-erasable ?ash code memory organized into 1 kb sectors and 64-byte pages. single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 256-byte ram data memory. n two analog comparators with selectable inputs and reference source. n two 16-bit counter/timers (each may be con?gured to toggle a port output upon timer over?ow or to become a pwm output). n a 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. n enhanced uart with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 khz byte-wide i 2 c-bus communication port and spi communication port. n 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). n enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. n 28-pin tssop and plcc packages with 23 i/o pins minimum and up to 26 i/o pins while using on-chip oscillator and reset options. 2.2 additional features n a high performance 80c51 cpu provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 mhz. this is six times the performance of the standard 80c51 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. n serial ?ash in-circuit programming (icp) allows simple production coding with commercial eprom programmers. flash security bits prevent reading of sensitive application programs. P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 4 kb/8 kb 3 v byte-erasable ?ash rev. 01 9 april 2009 preliminary data sheet
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 2 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core n serial ?ash in-system programming (isp) allows coding while the device is mounted in the end application. n in-application programming (iap) of the ?ash code memory. this allows changing the code in a running application. n watchdog timer with separate on-chip oscillator, nominal 400 khz, calibrated to 5%, requiring no external components. the watchdog prescaler is selectable from eight values. n high-accuracy internal rc oscillator option, with clock doubler option, allows operation without external oscillator components. the rc oscillator option is selectable and ?ne tunable. n switching on the ?y among internal rc oscillator, watchdog oscillator, external clock source provides optimal support of minimal power active mode with fast switching to maximum performance. n idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 m a (total power-down with voltage comparators disabled). n active-low reset. on-chip power-on reset allows operation without external reset components. a software reset function is also available. n con?gurable on-chip oscillator with frequency range options selected by user programmed ?ash con?guration bits. oscillator options support frequencies from 20 khz to the maximum operating frequency of 18 mhz. n oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. n programmable port output con?guration options: quasi-bidirectional, open drain, push-pull, input-only. n high current sourcing/sinking (20 ma) on eight i/o pins (p0.3 to p0.7, p1.4, p1.6, p1.7). all other port pins have high sinking capability (20 ma). a maximum limit is speci?ed for the entire chip. n port input pattern match detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. n only power and ground connections are required to operate the P89LPC9301/931a1 when internal reset option is selected. n four interrupt priority levels. n eight keypad interrupt inputs, plus two additional external interrupt inputs. n schmitt trigger port inputs. n second data pointer. n emulation support.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 3 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version P89LPC9301fdh tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 p89lpc931a1fdh tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 table 2. ordering options type number flash memory temperature range frequency P89LPC9301fdh 4 kb - 40 cto+85 c 0 mhz to 18 mhz p89lpc931a1fdh 8 kb - 40 cto+85 c 0 mhz to 18 mhz
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 4 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 4. block diagram fig 1. block diagram high performance accelerated 2-clock 80c51 cpu 4 kb/8 kb code flash 256-byte data ram port 2 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator with clock doubler internal bus crystal or resonator power monitor (power-on reset, brownout reset) 002aae447 analog comparators i 2 c-bus port 3 configurable i/os P89LPC9301/931a1 timer 0 timer 1 watchdog timer and oscillator p3[1:0] p2[7:0] port 1 configurable i/os p1[7:0] p0[7:0] xtal2 xtal1 scl sda txd rxd uart real-time clock/ system timer t0 t1 cmp2 cin2b cin2a cmp1 cin1a cin1b spi spiclk mosi miso ss
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 5 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 5. functional diagram fig 2. functional diagram v dd v ss port 0 port 3 txd rxd t0 int0 int1 rst scl sda 002aae448 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 mosi miso ss spiclk port 1 port 2 P89LPC9301/ 931a1 clkout
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 6 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 6. pinning information 6.1 pinning fig 3. P89LPC9301/931a1 tssop28 pin con?guration P89LPC9301fdh p89lpc931a1fdh 002aae451 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 p2.0 p2.1 p0.0/cmp2/kbi0 p1.7 p1.6 p1.5/rst v ss p3.1/xtal1 p3.0/xtal2/clkout p1.4/int1 p1.3/int0/sda p1.2/t0/scl p2.2/mosi p2.3/miso p2.7 p2.6 p0.1/cin2b/kbi1 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd p2.5/spiclk p2.4/ss
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 7 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 6.2 pin description table 3. pin description symbol pin type description p0.0 to p0.7 i/o port 0: port 0 is an 8-bit i/o port with a user-con?gurable output type. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 7.16.1 p or t con? gur ations and t ab le 10 static char acter istics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.0/cmp2/ kbi0 3 i/o p0.0 port 0 bit 0. o cmp2 comparator 2 output i kbi0 keyboard input 0. p0.1/cin2b/ kbi1 26 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. p0.2/cin2a/ kbi2 25 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. p0.3/cin1b/ kbi3 24 i/o p0.3 port 0 bit 3. high current source. i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. p0.4/cin1a/ kbi4 23 i/o p0.4 port 0 bit 4. high current source. i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. p0.5/cmpref/ kbi5 22 i/o p0.5 port 0 bit 5. high current source. i cmpref comparator reference (negative) input. i kbi5 keyboard input 5.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 8 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core p0.6/cmp1/kbi6 20 i/o p0.6 port 0 bit 6. high current source. o cmp1 comparator 1 output. i kbi6 keyboard input 6. p0.7/t1/kbi7 19 i/o p0.7 port 0 bit 7. high current source. i/o t1 timer/counter 1 external count input or over?ow output. i kbi7 keyboard input 7. p1.0 to p1.7 i/o, i [1] port 1: port 1 is an 8-bit i/o port with a user-con?gurable output type, except for three pins as noted below. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the con?gurable port 1 pins as inputs and outputs depends upon the port con?guration selected. each of the con?gurable port pins are programmed independently. refer to section 7.16.1 p or t con? gur ations and t ab le 10 static char acter istics for details. p1.2 to p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below: p1.0/txd 18 i/o p1.0 port 1 bit 0. o txd transmitter output for serial port. p1.1/rxd 17 i/o p1.1 port 1 bit 1. i rxd receiver input for serial port. p1.2/t0/scl 12 i/o p1.2 port 1 bit 2 (open-drain when used as output). i/o t0 timer/counter 0 external count input or over?ow output (open-drain when used as output). i/o scl i 2 c-bus serial clock input/output. p1.3/ int0/sda 11 i/o p1.3 port 1 bit 3 (open-drain when used as output). i int0 external interrupt 0 input. i/o sda i 2 c-bus serial data input/output. p1.4/ int1 10 i/o p1.4 port 1 bit 4. high current source. i int1 external interrupt 1 input. p1.5/ rst 6 i p1.5 port 1 bit 5 (input only). i rst external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used during a power-on sequence to force isp mode. p1.6 5 i/o p1.6 port 1 bit 6. high current source. p1.7 4 i/o p1.7 port 1 bit 7. high current source. p2.0 to p2.7 i/o port 2: port 2 is an 8-bit i/o port with a user-con?gurable output type. during reset port 2 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 2 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 7.16.1 p or t con? gur ations and t ab le 10 static char acter istics for details. all pins have schmitt trigger inputs. port 2 also provides various special functions as described below: p2.0 1 i/o p2.0 port 2 bit 0. p2.1 2 i/o p2.1 port 2 bit 1. table 3. pin description continued symbol pin type description
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 9 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] input/output for p1.0 to p1.4, p1.6, p1.7. input for p1.5. p2.2/mosi 13 i/o p2.2 port 2 bit 2. i/o mosi spi master out slave in. when con?gured as master, this pin is output; when con?gured as slave, this pin is input. p2.3/miso 14 i/o p2.3 port 2 bit 3. i/o miso when con?gured as master, this pin is input, when con?gured as slave, this pin is output. p2.4/ ss 15 i/o p2.4 port 2 bit 4. i ss spi slave select. p2.5/spiclk 16 i/o p2.5 port 2 bit 5. i/o spiclk spi clock. when con?gured as master, this pin is output; when con?gured as slave, this pin is input. p2.6 27 i/o p2.6 port 2 bit 6. p2.7 28 i/o p2.7 port 2 bit 7. p3.0 to p3.1 i/o port 3: port 3 is a 2-bit i/o port with a user-con?gurable output type. during reset port 3 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 3 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 7.16.1 p or t con? gur ations and t ab le 10 static char acter istics for details. all pins have schmitt trigger inputs. port 3 also provides various special functions as described below: p3.0/xtal2/ clkout 9 i/o p3.0 port 3 bit 0. o xtal2 output from the oscillator ampli?er (when a crystal oscillator option is selected via the ?ash con?guration. o clkout cpu clock divided by 2 when enabled via sfr bit (enclk -trim.6). it can be used if the cpu clock is the internal rc oscillator, watchdog oscillator or external clock input, except when xtal1/xtal2 are used to generate clock source for the rtc/system timer. p3.1/xtal1 8 i/o p3.1 port 3 bit 1. i xtal1 input to the oscillator circuit and internal clock generator circuits (when selected via the ?ash con?guration). it can be a port pin if internal rc oscillator or watchdog oscillator is used as the cpu clock source, and if xtal1/xtal2 are not used to generate the clock for the rtc/system timer. v ss 7i ground: 0 v reference. v dd 21 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 3. pin description continued symbol pin type description
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 10 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7. functional description remark: please refer to the P89LPC9301/931a1 user manual for a more detailed functional description. 7.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 11 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core table 4. special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 0000 00x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 0000 0000 brgr0 [2] baud rate generator 0 rate low beh 00 0000 0000 brgr1 [2] baud rate generator 0 rate high bfh 00 0000 0000 brgcon baud rate generator 0 control bdh - - - - - - sbrgs brgen 00 [2] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [1] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program ?ash address high e7h 00 0000 0000 fmadrl program ?ash address low e6h 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 12 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core fmcon program ?ash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program ?ash control (write) e4h fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 fmdata program ?ash data e5h 00 0000 0000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 0000 0000 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 0000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h - est - - espi ec ekbi ei2c 00 [1] 00x0 0000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x000 0000 table 4. special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 13 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core ip0h interrupt priority 0 high b7h - pwdrth pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h - pst - - pspi pc pkbi pi2c 00 [1] 00x0 0000 ip1h interrupt priority 1 high f7h - psth - - pspih pch pkbih pi2ch 00 [1] 00x0 0000 kbcon keypad control register 94h------patn _sel kbif 00 [1] xxxx xx00 kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kb7 cmp1 /kb6 cmpref /kb5 cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0/sda t0/scl rxd txd [1] bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h - - spiclk ss miso mosi - - [1] bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h - - - - - - xtal1 xtal2 [1] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 1111 1111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 0000 0000 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1 xx11 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0 xx00 table 4. special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 14 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core p2m1 port 2 output mode 1 a4h (p2m1.7) (p2m1.6) (p2m1.5) (p2m1.4) (p2m1.3) (p2m1.2) (p2m1.1) (p2m1.0) ff [1] 1111 1111 p2m2 port 2 output mode 2 a5h (p2m2.7) (p2m2.6) (p2m2.5) (p2m2.4) (p2m2.3) (p2m2.2) (p2m2.1) (p2m2.0) 00 [1] 0000 0000 p3m1 port 3 output mode 1 b1h - - - - - - (p3m1.1) (p3m1.0) 03 [1] xxxx xx11 p3m2 port 3 output mode 2 b2h - - - - - - (p3m2.1) (p3m2.0) 00 [1] xxxx xx00 pcon power control register 87h smod1 smod0 - boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd - vcpd - i2pd sppd spd - 00 [1] 0000 0000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x rstsrc reset source register dfh - boif bof pof r_bk r_wd r_sf r_ex [3] rtccon rtc control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1] [6] 011x xx00 rtch rtc register high d2h 00 [6] 0000 0000 rtcl rtc register low d3h 00 [6] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address 9f 9e 9d 9c 9b 9a 99 98 table 4. special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 15 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 0000 0100 spstat spi status register e1h spif wcol - - - - - - 00 00xx xxxx spdat spi data register e3h 00 0000 0000 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0 xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 0000 0000 trim internal oscillator trim register 96h rcclk enclk trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 4. special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 16 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] all ports are in input only (high-impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpre dictable. [3] the rstsrc register re?ects the cause of the P89LPC9301/931a1 reset except boif bit. upon a power-up reset, all reset source ?ags are cleared except pof and bof; the power-on reset value is x011 0000. [4] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 aft er power-on reset. other resets will not affect wdtof. [5] on power-on reset and watchdog reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initialization of the trim register. [6] the only reset sources that affect these sfrs are power-on reset and watchdog reset.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 17 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] extended sfrs are physically located on-chip but logically located in external data memory address space (xdata). the movx a,@dptr and movx @dptr ,a instructions are used to access these extended sfrs. [2] the boicfg1/0 will be copied from ucfg1.5 and ucfg1.3 when power-on reset. [3] clkcon register reset value comes from ucfg1 and ucfg2. the reset value of clkcon.2 to clkcon.0 come from ucfg1.2 to ucfg1.0 and reset value of clkdbl bit comes from ucfg2.7. table 5. extended special function registers [1] name description sfr addr. bit functions and addresses reset value msb lsb hex binary bodcfg bod con?guration register ffc8h ------ boicfg1 boicfg0 [2] clkcon clock control register ffdeh clkok - - xtalwd clkdbl fosc2 fosc1 fosc0 [3] rtcdath real-time clock data register high ffbfh 00 0000 0000 rtcdatl real-time clock data register low ffbeh 00 0000 0000
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 18 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.2 enhanced cpu the P89LPC9301/931a1 uses an enhanced 80c51 cpu which runs at six times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 7.3 clocks 7.3.1 clock de?nitions the P89LPC9301/931a1 device has several internal clocks as de?ned below: oscclk input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 4 ) and can also be optionally divided to a slower frequency (see section 7.11 cclk modi? cation: divm register ). remark: f osc is de?ned as the oscclk frequency. cclk cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk the internal 7.373 mhz rc oscillator output. the clock doubler option, when enabled, provides an output frequency of 14.746 mhz. pclk clock for the various peripheral devices and is cclk 2 . 7.3.2 cpu clock (oscclk) the P89LPC9301/931a1 provides several user-selectable oscillator options in generating the cpu clock. this allows optimization for a range of needs from high precision to lowest possible cost. these options are con?gured when the ?ash is programmed and include an on-chip watchdog oscillator, an on-chip rc oscillator, an oscillator using an external crystal, or an external clock source. 7.4 crystal oscillator option the crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 khz to 18 mhz. it can be the clock source of oscclk, rtc and wdt. 7.4.1 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. ceramic resonators are also supported in this con?guration. 7.4.2 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this con?guration. 7.4.3 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 18 mhz. ceramic resonators are also supported in this con?guration.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 19 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.5 clock output the P89LPC9301/931a1 supports a user-selectable clock output function on the p3.0/xtal2/clkout pin when crystal oscillator is not being used. this condition occurs if another clock source has been selected (on-chip rc oscillator, watchdog oscillator, external clock input on xtal1) and if the rtc and wdt are not using the crystal oscillator as their clock source. this allows external devices to synchronize to the P89LPC9301/931a1. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 2 that of the cclk. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 7.6 on-chip rc oscillator option the P89LPC9301/931a1 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 mhz 1 % at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies. when the clock doubler option is enabled (ucfg2.7 = 1), the output frequency is 14.746 mhz. if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to reduce power consumption. on reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. when clock doubler option is enabled, boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are required to hold the device in reset at power-up until v dd has reached its speci?ed level. 7.7 watchdog oscillator option the watchdog has a separate oscillator which has a frequency of 400 khz, calibrated to 5 % at room temperature. this oscillator can be used to save power when a high clock frequency is not needed. 7.8 external clock input option in this con?guration, the processor clock is derived from an external source driving the p3.1/xtal1 pin. the rate may be from 0 hz up to 18 mhz. the p3.0/xtal2/clkout pin may be used as a standard port pin or a clock output. when using an oscillator frequency above 12 mhz, boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are required to hold the device in reset at power-up until v dd has reached its speci?ed level. 7.9 clock sources switch on the ?y P89LPC9301/931a1 can implement clock source switch in any sources of watchdog oscillator, 7 mhz/14 mhz internal rc oscillator, external clock source (external crystal or external clock input) during code is running. clkok bit in clkcon register is used to indicate the clock switch status. clkok is cleared when starting clock source switch and set when completed. notice that when clkok is 0, writing to clkcon register is not allowed.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 20 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.10 cclk wake-up delay the P89LPC9301/931a1 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. if the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 oscclk cycles plus 60 m sto100 m s. if the clock source is the internal rc oscillator, the delay is 200 m sto 300 m s. if the clock source is watchdog oscillator or external clock, the delay is 32 oscclk cycles. 7.11 cclk modi?cation: divm register the oscclk frequency can be divided down up to 510 times by con?guring a dividing register, divm, to generate cclk. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow bypassing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. 7.12 low power select the P89LPC9301/931a1 is designed to run at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to lower the power consumption further. on any reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. fig 4. block diagram of oscillator control ? 2 002aae452 rtc cpu wdt divm cclk uart oscclk i 2 c-bus pclk timer 0 and timer 1 high frequency medium frequency low frequency xtal1 xtal2 rc oscillator with clock doubler watchdog oscillator (7.3728 mhz/14.7456 mhz 1 %) pclk rcclk spi (400 khz 5 %)
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 21 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.13 memory organization the various P89LPC9301/931a1 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? i data indirect data. 256 bytes of internal data memory space (00h:ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr special function registers. selected cpu registers and peripheral control and status registers, accessible only via direct addressing. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the P89LPC9301/931a1 has 4 kb/8 kb of on-chip code memory. 7.14 data ram arrangement the 256 bytes of on-chip ram are organized as shown in t ab le 6 . 7.15 interrupts the P89LPC9301/931a1 uses a four priority level interrupt structure. this allows great ?exibility in controlling the handling of the many interrupt sources. the P89LPC9301/931a1 supports 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/rtc, i 2 c-bus, keyboard, comparators 1 and 2, spi. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1 and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. if two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. table 6. on-chip data memory usages type data ram size (bytes) data memory that can be addressed directly and indirectly 128 idata memory that can be addressed indirectly 256
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 22 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.15.1 external interrupt inputs the P89LPC9301/931a1 has two external interrupt inputs as well as the keypad interrupt function. the two interrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request ?ag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the P89LPC9301/931a1 is put into power-down or idle mode, the interrupt will cause the processor to wake-up and resume operation. refer to section 7.18 p o w er reduction modes for details. fig 5. interrupt sources, interrupt enables, and power-down wake-up sources 002aae453 ie0 ex0 ie1 ex1 boif ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf1 et1 ti and ri/ri es/esr ti est si ei2c spif espi rtcf ertc (rtccon.1) wdovf tf0 et0
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 23 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.16 i/o ports the P89LPC9301/931a1 has four i/o ports: port 0, port 1, port 2 and port 3. ports 0, 1, and 2 are 8-bit ports, and port 3 is a 2-bit port. the exact number of i/o pins available depends upon the clock and reset options chosen, as shown in t ab le 7 . 7.16.1 port con?gurations all but three i/o port pins on the P89LPC9301/931a1 may be con?gured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input-only. two con?guration registers for each port select the output type for each port pin. 1. p1.5 ( rst) can only be an input and cannot be con?gured. 2. p1.2 (scl/t0) and p1.3 (sda/ int0) may only be con?gured to be either input-only or open-drain. 7.16.1.1 quasi-bidirectional output con?guration quasi-bidirectional output type can be used as both an input and output without the need to recon?gure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the P89LPC9301/931a1 is a 3 v device, but the pins are 5 v-tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current ?owing from the pin to v dd , causing extra power consumption. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt trigger input that also has a glitch suppression circuit. 7.16.1.2 open-drain output con?guration the open-drain output con?guration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . table 7. number of i/o pins available clock source reset option number of i/o pins (28-pin package) on-chip oscillator or watchdog oscillator no external reset (except during power-up) 26 external rst pin supported 25 external clock input no external reset (except during power-up) 25 external rst pin supported 24 low/medium/high speed oscillator (external crystal or resonator) no external reset (except during power-up) 24 external rst pin supported 23
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 24 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core an open-drain port pin has a schmitt trigger input that also has a glitch suppression circuit. 7.16.1.3 input-only con?guration the input-only port con?guration has no output drivers. it is a schmitt trigger input that also has a glitch suppression circuit. 7.16.1.4 push-pull output con?guration the push-pull output con?guration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt triggered input that also has a glitch suppression circuit. the P89LPC9301/931a1 device has high current source on eight pins in push-pull mode. see t ab le 9 limiting v alues . 7.16.2 port 0 analog functions the P89LPC9301/931a1 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high-impedance) mode. digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad[1:5] defaults to logic 0s to enable digital functions. 7.16.3 additional port features after power-up, all pins are in input-only mode. please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be con?gured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 are con?gurable for either input-only or open-drain. every output on the P89LPC9301/931a1 has been designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to t ab le 10 static char acter istics for detailed speci?cations. all ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. the slew rate is factory-set to approximately 10 ns rise and fall times. 7.17 power monitoring functions the P89LPC9301/931a1 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 25 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.17.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. enhanced brownout detection has 3 independent functions: bod reset, bod interrupt and bod flash. bod reset is always on except in total power-down mode. it could not be disabled in software. bod interrupt may be enabled or disabled in software. bod flash is always on, except in power-down modes and could not be disabled in software. bod reset and bod interrupt, each has four trip voltage levels. boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are used as trip point con?guration bits of bod reset. boicfg1 bit and boicfg0 bit in register bodcfg are used as trip point con?guration bits of bod interrupt. bod reset voltage should be lower than bod interrupt trip point. bod flash is used for ?ash programming/erase protection and has only 1 trip voltage of 2.4 v. please refer to P89LPC9301/931a1 user manual for detail con?gurations. if brownout detection is enabled the brownout condition occurs when v dd falls below the brownout trip voltage and is negated when v dd rises above the brownout trip voltage. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see t ab le 10 static char acter istics for speci?cations. 7.17.2 power-on detection the power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof ?ag in the rstsrc register is set to indicate an initial power-up condition. the pof ?ag will remain set until cleared by software. 7.18 power reduction modes the P89LPC9301/931a1 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode. 7.18.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. 7.18.2 power-down mode the power-down mode stops the oscillator in order to minimize power consumption. the P89LPC9301/931a1 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the data retention supply voltage v ddr . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ddr , therefore it is highly recommended to wake-up the processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and rtc/system timer. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 26 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.18.3 total power-down mode this is the same as power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. if the internal rc oscillator is used to clock the rtc during power-down, there will be high power consumption. please use an external low frequency clock to achieve low power with the rtc running during power-down. 7.19 reset the p1.5/ rst pin can function as either a low-active reset input or as a digital input, p1.5. the reset pin enable (rpe) bit in ucfg1, when set to logic 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin always functions as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this pin will function as de?ned by the rpe bit. only a power-up reset will temporarily override the selection de?ned by rpe bit. other sources of reset will not override the rpe bit. note: during a power cycle, v dd must fall below v por before power is reapplied, in order to ensure a power-on reset (see t ab le 10 static char acter istics ). reset can be triggered from the following sources: ? external reset pin (during power-up or if user con?gured via ucfg1) ? power-on detect ? brownout detect ? watchdog timer ? software reset ? uart break character detect reset for every reset source, there is a ?ag in the reset register, rstsrc. the user can read this register to determine the most recent reset source. these ?ag bits can be cleared in software by writing a logic 0 to the corresponding bit. more than one ?ag bit may be set: ? during a power-on reset, both pof and bof are set but the other ?ag bits are cleared. ? a watchdog reset is similar to a power-on reset, both pof and bof are set but the other ?ag bits are cleared. ? for any other reset, previously set ?ag bits that have not been cleared will remain set. 7.19.1 reset vector following reset, the P89LPC9301/931a1 will fetch instructions from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 27 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core the boot address will be used if a uart break reset occurs, or the non-volatile boot status bit (boots tat.0) = 1, or the device is forced into isp mode during power-on (see P89LPC9301/931a1 user manual ). otherwise, instructions will be fetched from address 0000h. 7.20 timers/counters 0 and 1 the P89LPC9301/931a1 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be con?gured to operate either as timers or event counters. an option to automatically toggle the t0 and/or t1 pins upon timer over?ow has been added. in the timer function, the register is incremented every machine cycle. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. timer 0 and timer 1 have ?ve operating modes (modes 0, 1, 2, 3 and 6). modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 7.20.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is con?gured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 7.20.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 7.20.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 7.20.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the serial port as a baud rate generator. 7.20.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 7.20.6 timer over?ow toggle output timers 0 and 1 can be con?gured to automatically toggle a port output whenever a timer over?ow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. the port outputs will be a logic 1 prior to the ?rst timer over?ow when this mode is turned on.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 28 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.21 rtc/system timer the P89LPC9301/931a1 has a simple rtc that allows a user to continue running an accurate timer while the rest of the device is powered down. the rtc can be a wake-up or an interrupt source. the rtc is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. when it reaches all logic 0s, the counter will be reloaded again and the rtcf ?ag will be set. the clock source for this counter can be either the cpu clock (cclk) or the xtal oscillator. only power-on reset and watchdog reset will reset the rtc and its associated sfrs to the default state. the 16-bit loadable counter portion of the rtc is readable by reading the rtcdatl and rtcdath registers. 7.22 uart the P89LPC9301/931a1 has an enhanced uart that is compatible with the conventional 80c51 uart except that timer 2 over?ow cannot be used as a baud rate source. the P89LPC9301/931a1 does include an independent baud rate generator. the baud rate can be selected from the oscillator (divided by a constant), timer 1 over?ow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable double buffering and several interrupt options. the uart can be operated in four modes: shift register, 8-bit uart, 9-bit uart, and cpu clock/32 or cpu clock/16. 7.22.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 16 of the cpu clock frequency. 7.22.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), and a stop bit (logic 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 7.22.5 baud r ate gener ator and selection ). 7.22.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logic 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of logic 0 or logic 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 29 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.22.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 7.22.5 baud r ate gener ator and selection ). 7.22.5 baud rate generator and selection the P89LPC9301/931a1 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1 but is much more accurate. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 6 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generators use oscclk. 7.22.6 framing error framing error is reported in the status register (sstat). in addition, if smod0 (pcon.6) is logic 1, framing errors can be made available in scon.7 respectively. if smod0 is logic 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is logic 0. 7.22.7 break detect break detect is reported in the status register (sstat). a break is detected when 11 consecutive bits are sensed low. the break detect can be used to reset the device and force the device into isp mode. 7.22.8 double buffering the uart has a transmit double buffer that allows buffering of the next character to be written to snbuf while the ?rst character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. double buffering can be disabled. if disabled (dbmod, i.e., ss tat. 7 = 0), the uart is compatible with the conventional 80c51 uart. if enabled, the uart allows writing to sbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). fig 6. baud rate sources for uart (modes 1, 3) baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa897 ? 2
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 30 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.22.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the ti interrupt is generated when the double buffer is ready to receive new data. 7.22.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as indicated by the ti interrupt. if double buffering is enabled, tb8 must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data. 7.23 i 2 c-bus serial interface the i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multi master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus con?guration is shown in figure 7 . the P89LPC9301/931a1 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 7. i 2 c-bus con?guration other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl P89LPC9301/931a1 i 2 c-bus 002aae455
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 31 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core fig 8. i 2 c-bus serial interface block diagram internal bus 002aaa899 address register comparator shift register 8 i2adr ack bit counter / arbitration and sync logic 8 i2dat timing and control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers and scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 32 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.24 spi the P89LPC9301/931a1 provides another high-speed serial communication interface: the spi interface. spi is a full-duplex, high-speed, synchronous communication bus with two operation modes: master mode and slave mode. up to 3 mbit/s can be supported in either master mode or slave mode. it has a transfer completion flag and write collision flag protection. the spi interface has four pins: spiclk, mosi, miso and ss: ? spiclk, mosi and miso are typically tied together between two or more spi devices. data ?ows from master to slave on mosi (master out slave in) pin and ?ows from slave to master on miso (master in slave out) pin. the spiclk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (reset value), these pins are con?gured for port functions. ? ss is the optional slave select pin. in a typical con?guration, an spi master asserts one of its port pins to select one spi device as the current slave. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figure 10 through figure 12 . fig 9. spi block diagram 002aaa900 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p2.3 mosi p2.2 spiclk p2.5 ss p2.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 33 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.24.1 typical spi con?gurations fig 10. spi single master single slave con?guration fig 11. spi dual device con?guration, where either can be a master or a slave 002aaa901 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa902 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 34 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.25 analog comparators two analog comparators are provided on the P89LPC9301/931a1. input and output options allow use of the comparators in a number of different con?gurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be con?gured to cause an interrupt when the output value changes. the overall connections to both comparators are shown in figure 13 . the comparators function to v dd = 2.4 v. when each comparator is ?rst enabled, the comparator output and interrupt ?ag are not guaranteed to be stable for 10 m s. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ?ag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparators output, con, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator ?ag, cmfn. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator ?ag, cmfn, after disabling the comparator. fig 12. spi single master multiple slaves con?guration 002aaa903 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 35 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.25.1 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref(bg) , is 1.23 v 10 %. 7.25.2 comparator interrupt each comparator has an interrupt ?ag contained in its con?guration register. this ?ag is set whenever the comparator output changes state. the ?ag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ?ags to determine which comparator caused the interrupt. 7.25.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. if the comparator output to a pin is enabled, the pin should be con?gured in the push-pull mode in order to obtain fast switching times while in power-down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. fig 13. comparator input and output connections comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref(bg) oe1 co1 cmf1 interrupt 002aae456 cmp1 (p0.6) ec cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b change detect change detect
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 36 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.26 kbi the keypad interrupt function (kbi) is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can con?gure the port via sfrs for different tasks. the keypad interrupt mask register (kbmask) is used to de?ne which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to de?ne a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrupt control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrupt will be generated if enabled. the patn_sel bit in the keypad interrupt control register (kbcon) is used to de?ne equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in p87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by the kbmask register will cause the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake-up the cpu from idle or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the ?ag and cause an interrupt, the pattern on port 0 must be held longer than six cclks. 7.27 watchdog timer the watchdog timer causes a system reset when it under?ows as a result of a failure to feed the timer prior to the timer reaching its terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler can be the pclk, the nominal 400 khz watchdog oscillator or crystal oscillator. the watchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 14 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few m s to a few seconds. please refer to the P89LPC9301/931a1 user manual for more details.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 37 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.28 additional features 7.28.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 7.28.2 dual data pointers the dual data pointers (dptr) provides two different data pointers to specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is permanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. 7.29 flash program memory 7.29.1 general description the P89LPC9301/931a1 ?ash memory provides in-circuit electrical erasure and programming. the ?ash can be erased, read, and written as bytes. the sector and page erase functions can erase any ?ash sector (1 kb) or page (64 bytes). the chip erase operation will erase the entire program memory. icp using standard commercial programmers is available. in addition, iap and byte-erase allows code memory to be used for non-volatile data storage. on-chip erase and write timing generation contribute to a user-friendly programming interface. the P89LPC9301/931a1 ?ash reliably stores memory contents even after 100,000 erase and program cycles. the cell is designed to (1) watchdog reset can also be caused by an invalid feed sequence, or by writing to wdcon not immediately followed by a feed sequence. fig 14. watchdog timer in watchdog mode (wdte = 1) pre2 pre1 pre0 - - wdrun wdtof wdclk wdcon (a7h) shadow register prescaler 002aae015 8-bit down counter wdl (c1h) watchdog oscillator crystal oscillator pclk xtalwd ? 32 0 1 0 1 mov wfeed1, #0a5h mov wfeed2, #05ah reset (1)
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 38 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core optimize the erase and programming mechanisms. the P89LPC9301/931a1 uses v dd as the supply voltage to perform the program/erase algorithms. when voltage supply is lower than 2.4 v, the bod flash is tripped and ?ash erase/program is blocked. 7.29.2 features ? programming and erase over the full operating voltage range. ? byte erase allows code memory to be used for data storage. ? read/programming/erase using isp/iap/icp. ? internal ?xed boot rom, containing low-level iap routines available to user code. ? default loader providing isp via the serial port, located in upper end of user program memory. ? boot vector allows user-provided ?ash loader code to reside anywhere in the ?ash memory space, providing ?exibility to the user. ? any ?ash program/erase operation in 2 ms. ? programming with industry-standard commercial programmers. ? programmable security for the code in the ?ash for each sector. ? 100,000 typical erase/program cycles for each byte. ? 10 year minimum data retention. 7.29.3 flash organization the program memory consists of four/eight 1 kb sectors on the P89LPC9301/931a1 devices. each sector can be further divided into 64-byte pages. in addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. 7.29.4 using ?ash as data storage the ?ash code memory array of this device supports individual byte erasing and programming. any byte in the code memory array may be read using the movc instruction, provided that the sector containing the byte has not been secured (a movc instruction is not allowed to read code memory contents of a secured sector). thus any byte in a non-secured sector may be used for non-volatile data storage. 7.29.5 flash programming and erasing four different methods of erasing or programming of the ?ash are available. the ?ash may be programmed or erased in the end-user application (iap) under control of the applications ?rmware. another option is to use the icp mechanism. this icp system provides for programming through a serial clock/serial data interface. as shipped from the factory, the upper 512 bytes of user code space contains a serial isp routine allowing for the device to be programmed in circuit through the serial port. the ?ash may also be programmed or erased using a commercially available eprom programmer which supports this device. this device does not provide for direct veri?cation of code memory contents. instead, this device provides a 32-bit crc result on either a sector or the entire user code space. remark: when voltage supply is lower than 2.4 v, the bod flash is tripped and ?ash erase/program is blocked.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 39 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 7.29.6 icp icp is performed without removing the microcontroller from the system. the icp facility consists of internal hardware resources to facilitate remote programming of the P89LPC9301/931a1 through a two-wire serial interface. the nxp icp facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. the icp function uses ?ve pins. only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. additional details may be found in the P89LPC9301/931a1 user manual . 7.29.7 iap iap is performed in the application under the control of the microcontrollers ?rmware. the iap facility consists of internal hardware resources to facilitate programming and erasing. the nxp iap has made in-application programming in an embedded application possible without additional components. two methods are available to accomplish iap. a set of prede?ned iap functions are provided in a boot rom and can be called through a common interface, pgm_mtp. several iap calls are available for use by an application program to permit selective erasing and programming of ?ash sectors, pages, security bits, con?guration bytes, and device id. these functions are selected by setting up the microcontrollers registers before making a call to pgm_mtp at ff03h. the boot rom occupies the program memory space at the top of the address space from ff00h to feffh, thereby not con?icting with the user program memory space. in addition, iap operations can be accomplished through the use of four sfrs consisting of a control/status register, a data register, and two address registers. additional details may be found in the P89LPC9301/931a1 user manual . 7.29.8 isp isp is performed without removing the microcontroller from the system. the isp facility consists of a series of internal hardware resources coupled with internal ?rmware to facilitate remote programming of the P89LPC9301/931a1 through the serial port. this ?rmware is provided by nxp and embedded within each P89LPC9301/931a1 device. the nxp isp facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses ?ve pins (v dd , v ss , txd, rxd, and rst). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 7.29.9 power-on reset code execution the P89LPC9301/931a1 contains two special ?ash elements: the boot vector and the boot status bit. following reset, the P89LPC9301/931a1 examines the contents of the boot status bit. if the boot status bit is set to zero, power-up execution starts at location 0000h, which is the normal start address of the users application code. when the boot status bit is set to a value other than zero, the contents of the boot vector are used as the high byte of the execution address and the low byte is set to 00h. t ab le 8 shows the factory default boot vector setting for these devices. a factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform isp functions. this code can be erased by the user.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 40 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core remark: users who wish to use this loader should take precautions to avoid erasing the 1 kb sector that contains this bootloader. instead, the page erase function can be used to erase the ?rst eight 64-byte pages located in this sector. a custom bootloader can be written with the boot vector set to the custom bootloader, if desired. 7.29.10 hardware activation of the bootloader the bootloader can also be executed by forcing the device into isp mode during a power-on sequence (see the P89LPC9301/931a1 user manual for speci?c information). this has the same effect as having a non-zero status byte. this allows an application to be built that will normally execute user code but can be manually forced into isp operation. if the factory default setting for the boot vector is changed, it will no longer point to the factory pre-programmed isp bootloader code. after programming the ?ash, the status byte should be programmed to zero in order to allow execution of the users application code beginning at address 0000h. 7.30 user con?guration bytes some user-con?gurable features of the P89LPC9301/931a1 must be de?ned at power-up and therefore cannot be set by the program after start of execution. these features are con?gured through the use of the ?ash byte ucfg1 and ucfg2. please see the P89LPC9301/931a1 user manual for additional details. 7.31 user sector security bytes there are four/eight user sector security bytes on the P89LPC9301/931a1. each byte corresponds to one sector. please see the P89LPC9301/931a1 user manual for additional details. table 8. default boot vector values and isp entry points device default boot vector default bootloader entry point default bootloader code range 1 kb sector range P89LPC9301 0fh 0f00h 0e00h to 0fffh 0c00h to 0fffh p89lpc931a1 1fh 1f00h 1e00h to 1fffh 1c00h to 1fffh
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 41 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 8. limiting values [1] the following applies to t ab le 9 : a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over ambient temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 9. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit t amb(bias) bias ambient temperature - 55 +125 c t stg storage temperature - 65 +150 c i oh(i/o) high-level output current per input/output pin -20ma i ol(i/o) low-level output current per input/output pin -20ma i i/otot(max) maximum total input/output current - 100 ma v n voltage on any other pin except v ss , with respect to v dd - 3.5 v p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [2] - 2000 +2000 v charged device model; all pins - 500 +500 v fig 15. frequency vs. supply voltage v dd (v) 002aae351 system frequency (mhz) 2.4 18 12 2.7 3.6 3.3 3.0
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 42 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 9. static characteristics table 10. static characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd(oper) operating supply current v dd = 3.6 v; f osc =12mhz [2] -1015ma v dd = 3.6 v; f osc =18mhz [2] -1423ma i dd(idle) idle mode supply current v dd = 3.6 v; f osc =12mhz [3] - 3.25 5 ma v dd = 3.6 v; f osc =18mhz [3] -57ma i dd(pd) power-down mode supply current v dd = 3.6 v; voltage comparators powered down [4] -2040 m a i dd(tpd) total power-down mode supply current v dd = 3.6 v [5] -15 m a (dv/dt) r rise rate of v dd ; to ensure power-on reset signal 5 - 5000 v/s v ddr data retention supply voltage 1.5 - - v v th(hl) high-low threshold voltage except scl, sda 0.22v dd 0.4v dd -v v il low-level input voltage scl, sda only - 0.5 - 0.3v dd v v th(lh) low-high threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih high-level input voltage scl, sda only 0.7v dd - 5.5 v v hys hysteresis voltage port 1 - 0.2v dd -v v ol low-level output voltage i ol = 20 ma; v dd = 2.4 v to 3.6 v all ports, all modes except high-z [6] - 0.6 1.0 v i ol = 3.2 ma; v dd = 2.4 v to 3.6 v all ports, all modes except high-z [6] - 0.2 0.3 v v oh high-level output voltage i oh = - 20 m a; v dd = 2.4 v to 3.6 v; all ports, quasi-bidirectional mode v dd - 0.3 v dd - 0.2 - v i oh = - 3.2 ma; v dd = 2.4 v to 3.6 v; all ports, push-pull mode v dd - 0.7 v dd - 0.4 - v i oh = - 10 ma; v dd = 2.4 v to 3.6 v; all ports, push-pull mode - 3.2 - v v xtal crystal voltage on xtal1, xtal2 pins; with respect to v ss - 0.5 - +4.0 v v n voltage on any other pin except xtal1, xtal2, v dd ; with respect to v ss [7] - 0.5 - +5.5 v c iss input capacitance [8] - - 15 pf i il low-level input current v i = 0.4 v [9] -- - 80 m a i li input leakage current v i =v il , v ih , or v th(hl) [10] -- 1 m a
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 43 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. [2] the i dd(oper) speci?cation is measured using an external clock with code while(1) {} executed from on-chip ?ash. [3] the i dd(idle) speci?cation is measured using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. [4] the i dd(pd) speci?cation is measured using internal rc oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. [5] the i dd(tpd) speci?cation is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. [6] see section 8 limiting v alues for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related speci?cation. [7] this speci?cation can be applied to pins which have a/d input or analog comparator input functions when the pin is not being used for those analog functions. when the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 v with respect to v ss . [8] pin capacitance is characterized but not tested. [9] measured with port in quasi-bidirectional mode. [10] measured with port in high-impedance mode. [11] port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. th is current is highest when v i is approximately 2 v. i thl high-low transition current all ports; v i = 1.5 v at v dd = 3.6 v [11] - 30 - - 450 m a r rst_n(int) internal pull-up resistance on pin rst pin rst 10 - 30 k w v ref(bg) band gap reference voltage 1.11 1.23 1.34 v tc bg band gap temperature coef?cient - 10 20 ppm/ c table 10. static characteristics continued v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 44 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 9.1 current characteristics note: the graphs provided are a statistical summary based on a limited number of samples and only for information purposes. the performance characteristics listed are not tested or guaranteed. test conditions: normal mode, code while(1) {} executed from on-chip ?ash; using an external clock. fig 16. i dd(oper) vs. frequency at +25 c test conditions: normal mode, code while(1) {} executed from on-chip ?ash; using an external clock. fig 17. i dd(oper) vs. frequency at - 40 c v dd (v) 2.4 3.6 3.2 2.8 002aae363 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae364 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 45 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core test conditions: normal mode, code while(1) {} executed from on-chip ?ash; using an external clock. fig 18. i dd(oper) vs. frequency at +85 c test conditions: idle mode entered executing code from on-chip ?ash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. fig 19. i dd(idle) vs. frequency at +25 c v dd (v) 2.4 3.6 3.2 2.8 002aae365 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae366 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 46 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core test conditions: idle mode entered executing code from on-chip ?ash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. fig 20. i dd(idle) vs. frequency at - 40 c test conditions: idle mode entered executing code from on-chip ?ash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. fig 21. i dd(idle) vs. frequency at +85 c v dd (v) 2.4 3.6 3.2 2.8 002aae367 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae368 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 47 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core test conditions: power-down mode, using internal rc oscillator with the following functions disabled: comparators, real-time clock, and watchdog timer. (1) +85 c (2) +25 c (3) - 40 c fig 22. i dd(pd) vs. v dd test conditions: total power-down mode, using internal rc oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. (1) +85 c (2) - 40 c (3) +25 c fig 23. i dd(tpd) vs. v dd v dd (v) 2.4 3.6 3.2 2.8 002aae369 14.0 16.0 12.0 18.0 20.0 i dd ( m a) 10.0 (2) (3) (1) v dd (v) 2.4 3.6 3.2 2.8 002aae370 0.4 0.8 1.2 i dd ( m a) 0.0 (1) (2) (3)
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 48 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 9.2 internal rc/watchdog oscillator characteristics note: the graphs provided are a statistical summary based on a limited number of samples and only for information purposes. the performance characteristics listed are not tested or guaranteed. central frequency of internal rc oscillator = 7.3728 mhz fig 24. average internal rc oscillator frequency vs. v dd at +25 c note: central frequency of internal rc oscillator = 7.3728 mhz fig 25. average internal rc oscillator frequency vs. v dd at - 40 c v dd (v) 2.4 3.6 3.2 2.8 002aae344 0 - 0.1 0.1 0.2 frequency deviation (%) - 0.2 v dd (v) 2.4 3.6 3.2 2.8 002aae346 0 - 0.1 0.1 0.2 frequency deviation (%) - 0.2
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 49 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core central frequency of internal rc oscillator = 7.3728 mhz fig 26. average internal rc oscillator frequency vs. v dd at +85 c central frequency of watchdog oscillator = 400 khz fig 27. average watchdog oscillator frequency vs. v dd at +25 c v dd (v) 2.4 3.6 3.2 2.8 002aae347 - 0.2 - 0.4 0 0.2 frequency deviation (%) - 0.6 v dd (v) 2.4 3.6 3.2 2.8 002aae348 0.5 - 0.5 1.5 2.5 frequency deviation (%) - 1.5
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 50 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core central frequency of watchdog oscillator = 400 khz fig 28. average watchdog oscillator frequency vs. v dd at - 40 c central frequency of watchdog oscillator = 400 khz fig 29. average watchdog oscillator frequency vs. v dd at +85 c v dd (v) 2.4 3.6 3.2 2.8 002aae349 - 1.5 - 2.5 - 0.5 0.5 frequency deviation (%) - 3.5 v dd (v) 2.4 3.6 3.2 2.8 002aae350 - 0.5 - 1.5 0.5 1.5 frequency deviation (%) - 2.5
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 51 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 9.3 bod characteristics [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. table 11. bod static characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit bod interrupt v trip trip voltage falling stage boicfg1, boicfg0 = 01 2.25 - 2.55 v boicfg1, boicfg0 = 10 2.60 - 2.80 v boicfg1, boicfg0 = 11 3.10 - 3.40 v rising stage boicfg1, boicfg0 = 01 2.30 - 2.60 v boicfg1, boicfg0 = 10 2.70 - 2.90 v boicfg1, boicfg0 = 11 3.15 - 3.45 v bod reset v trip trip voltage falling stage boe1, boe0 = 01 2.10 - 2.30 v boe1, boe0 = 10 2.25 - 2.55 v boe1, boe0 = 11 2.80 - 3.20 v rising stage boe1, boe0 = 01 2.20 - 2.40 v boe1, boe0 = 10 2.30 - 2.60 v boe1, boe0 = 11 2.90 - 3.30 v bod eeprom/?ash v trip trip voltage falling stage 2.25 - 2.55 v rising stage 2.30 - 2.60 v fig 30. bod interrupt/reset characteristics v dd v trip 002aae352 (bof/boif set by hardware) (bof/boif can be cleared in software) bof/boif
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 52 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 10. dynamic characteristics table 12. dynamic characteristics (12 mhz) v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. [1] [2] symbol parameter conditions variable clock f osc = 12 mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1 % at t amb =25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on, v dd = 2.7 v to 3.6 v 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency t amb =25 c 380 420 380 420 khz f osc oscillator frequency 0 12 - - mhz t cy(clk) clock cycle time see figure 32 83 - - - ns f clklp low-power select clock frequency 0 8 - - mhz glitch ?lter t gr glitch rejection time p1.5/ rst pin - 50 - 50 ns any pin except p1.5/ rst - 15 - 15 ns t sa signal acceptance time p1.5/ rst pin 125 - 125 - ns any pin except p1.5/ rst 50 - 50 - ns external clock t chcx clock high time see figure 32 33 t cy(clk) - t clcx 33 - ns t clcx clock low time see figure 32 33 t cy(clk) - t chcx 33 - ns t clch clock rise time see figure 32 -8-8ns t chcl clock fall time see figure 32 -8-8ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 31 16t cy(clk) - 1333 - ns t qvxh output data set-up to clock rising edge time see figure 31 13t cy(clk) - 1083 - ns t xhqx output data hold after clock rising edge time see figure 31 -t cy(clk) + 20 - 103 ns t xhdx input data hold after clock rising edge time see figure 31 -0-0ns t xhdv input data valid to clock rising edge time see figure 31 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk 6 0 2.0 mhz master - cclk 4 - 3.0 mhz
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 53 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spicyc spi cycle time see figure 33 , 34 , 35 , 36 slave 6 cclk - 500 - ns master 4 cclk - 333 - ns t spilead spi enable lead time see figure 35 , 36 slave 250 - 250 - ns t spilag spi enable lag time see figure 35 , 36 slave 250 - 250 - ns t spiclkh spiclk high time see figure 33 , 34 , 35 , 36 master 2 cclk - 165 - ns slave 3 cclk - 250 - ns t spiclkl spiclk low time see figure 33 , 34 , 35 , 36 master 2 cclk - 165 - ns slave 3 cclk - 250 - ns t spidsu spi data set-up time see figure 33 , 34 , 35 , 36 100 - 100 - ns master or slave t spidh spi data hold time see figure 33 , 34 , 35 , 36 100 - 100 - ns master or slave t spia spi access time see figure 35 , 36 slave 0 120 0 120 ns t spidis spi disable time see figure 35 , 36 slave 0 240 - 240 ns t spidv spi enable to output data valid time see figure 33 , 34 , 35 , 36 slave - 240 - 240 ns master - 167 - 167 ns t spioh spi output data hold time see figure 33 , 34 , 35 , 36 0-0-ns t spir spi rise time see figure 33 , 34 , 35 , 36 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif spi fall time see figure 33 , 34 , 35 , 36 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 12. dynamic characteristics (12 mhz) continued v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. [1] [2] symbol parameter conditions variable clock f osc = 12 mhz unit min max min max
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 54 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core table 13. dynamic characteristics (18 mhz) v dd = 3.0 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1 % at t amb =25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency t amb =25 c 380 420 380 420 khz f osc oscillator frequency 0 18 - - mhz t cy(clk) clock cycle time see figure 32 55 - - - ns f clklp low-power select clock frequency 0 8 - - mhz glitch ?lter t gr glitch rejection time p1.5/ rst pin - 50 - 50 ns any pin except p1.5/ rst - 15 - 15 ns t sa signal acceptance time p1.5/ rst pin 125 - 125 - ns any pin except p1.5/ rst 50 - 50 - ns external clock t chcx clock high time see figure 32 22 t cy(clk) - t clcx 22 - ns t clcx clock low time see figure 32 22 t cy(clk) - t chcx 22 - ns t clch clock rise time see figure 32 -5-5ns t chcl clock fall time see figure 32 -5-5ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 31 16t cy(clk) - 888 - ns t qvxh output data set-up to clock rising edge time see figure 31 13t cy(clk) - 722 - ns t xhqx output data hold after clock rising edge time see figure 31 -t cy(clk) + 20 - 75 ns t xhdx input data hold after clock rising edge time see figure 31 -0-0ns t xhdv input data valid to clock rising edge time see figure 31 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk 6 0 3.0 mhz master - cclk 4 - 4.5 mhz t spicyc spi cycle time see figure 33 , 34 , 35 , 36 slave 6 cclk - 333 - ns master 4 cclk - 222 - ns
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 55 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spilead spi enable lead time see figure 35 , 36 slave 250 - 250 - ns t spilag spi enable lag time see figure 35 , 36 slave 250 - 250 - ns t spiclkh spiclk high time see figure 33 , 34 , 35 , 36 slave 3 cclk - 167 - ns master 2 cclk - 111 - ns t spiclkl spiclk low time see figure 33 , 34 , 35 , 36 slave 3 cclk - 167 - ns master 2 cclk - 111 - ns t spidsu spi data set-up time see figure 33 , 34 , 35 , 36 master or slave 100 - 100 - ns t spidh spi data hold time see figure 33 , 34 , 35 , 36 master or slave 100 - 100 - ns t spia spi access time see figure 35 , 36 slave 0 80 0 80 ns t spidis spi disable time see figure 35 , 36 slave 0 160 - 160 ns t spidv spi enable to output data valid time see figure 33 , 34 , 35 , 36 slave - 160 - 160 ns master - 111 - 111 ns t spioh spi output data hold time see figure 33 , 34 , 35 , 36 0-0-ns t spir spi rise time see figure 33 , 34 , 35 , 36 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif spi fall time see figure 33 , 34 , 35 , 36 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 13. dynamic characteristics (18 mhz) continued v dd = 3.0 v to 3.6 v unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 56 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 10.1 waveforms fig 31. shift register mode timing 01234567 valid valid valid valid valid valid valid valid t xlxl 002aaa906 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 32. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 fig 33. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 57 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core fig 34. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 35. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spir t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 58 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 10.2 isp entry mode fig 36. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidsu t spidh t spidh t spir t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input) table 14. dynamic characteristics, isp entry mode v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. symbol parameter conditions min typ max unit t vr v dd active to rst active delay time pin rst 50 - - m s t rh rst high time pin rst 1 - 32 m s t rl rst low time pin rst 1 - - m s fig 37. isp entry waveform 002aaa912 v dd rst t rl t vr t rh
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 59 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 11. other characteristics 11.1 comparator electrical characteristics [1] this parameter is characterized, but not tested in production. table 15. comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 c to +85 c for industrial applications, unless otherwise speci?ed. symbol parameter conditions min typ max unit v io input offset voltage - - 20 mv v ic common-mode input voltage 0 - v dd - 0.3 v cmrr common-mode rejection ratio [1] -- - 50 db t res(tot) total response time - 250 500 ns t (ce-ov) chip enable to output valid time - - 10 m s i li input leakage current 0 v < v i P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 60 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 12. package outline fig 38. tssop package outline (sot361-1) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 114 28 15 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 61 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 13. abbreviations table 16. abbreviations acronym description bod brownout detection ccu capture/compare unit cpu central processing unit crc cyclic redundancy check dac digital to analog converter eprom erasable programmable read-only memory eeprom electrically erasable programmable read-only memory emi electro-magnetic interference pga programmable gain ampli?er pll phase-locked loop pwm pulse-width modulator ram random access memory rc resistance-capacitance rtc real-time clock sar successive approximation register sfr special function register spi serial peripheral interface uart universal asynchronous receiver/transmitter wdt watchdog timer
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 62 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 14. revision history table 17. revision history document id release date data sheet status change notice supersedes P89LPC9301_931a1_1 20090409 preliminary data sheet - -
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 63 of 65 nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
P89LPC9301_931a1_1 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 01 9 april 2009 64 of 65 continued >> nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 10 7.1 special function registers . . . . . . . . . . . . . . . . 10 7.2 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.1 clock de?nitions . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.2 cpu clock (oscclk). . . . . . . . . . . . . . . . . . . 18 7.4 crystal oscillator option . . . . . . . . . . . . . . . . . 18 7.4.1 low speed oscillator option . . . . . . . . . . . . . . 18 7.4.2 medium speed oscillator option . . . . . . . . . . . 18 7.4.3 high speed oscillator option . . . . . . . . . . . . . . 18 7.5 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.6 on-chip rc oscillator option . . . . . . . . . . . . . . 19 7.7 watchdog oscillator option . . . . . . . . . . . . . . . 19 7.8 external clock input option . . . . . . . . . . . . . . . 19 7.9 clock sources switch on the ?y. . . . . . . . . . . . 19 7.10 cclk wake-up delay . . . . . . . . . . . . . . . . . . . 20 7.11 cclk modi?cation: divm register . . . . . . . . . 20 7.12 low power select . . . . . . . . . . . . . . . . . . . . . . 20 7.13 memory organization . . . . . . . . . . . . . . . . . . . 21 7.14 data ram arrangement . . . . . . . . . . . . . . . . . 21 7.15 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15.1 external interrupt inputs . . . . . . . . . . . . . . . . . 22 7.16 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16.1 port con?gurations . . . . . . . . . . . . . . . . . . . . . 23 7.16.1.1 quasi-bidirectional output con?guration . . . . . 23 7.16.1.2 open-drain output con?guration . . . . . . . . . . . 23 7.16.1.3 input-only con?guration . . . . . . . . . . . . . . . . . 24 7.16.1.4 push-pull output con?guration . . . . . . . . . . . . 24 7.16.2 port 0 analog functions . . . . . . . . . . . . . . . . . . 24 7.16.3 additional port features. . . . . . . . . . . . . . . . . . 24 7.17 power monitoring functions. . . . . . . . . . . . . . . 24 7.17.1 brownout detection . . . . . . . . . . . . . . . . . . . . . 25 7.17.2 power-on detection . . . . . . . . . . . . . . . . . . . . . 25 7.18 power reduction modes . . . . . . . . . . . . . . . . . 25 7.18.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.18.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 25 7.18.3 total power-down mode . . . . . . . . . . . . . . . . . 26 7.19 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.19.1 reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.20 timers/counters 0 and 1 . . . . . . . . . . . . . . . . 27 7.20.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.20.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.20.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.20.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.20.5 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.20.6 timer over?ow toggle output . . . . . . . . . . . . . 27 7.21 rtc/system timer. . . . . . . . . . . . . . . . . . . . . . 28 7.22 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.22.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.22.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.22.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.22.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.22.5 baud rate generator and selection . . . . . . . . . 29 7.22.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.22.7 break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.22.8 double buffering . . . . . . . . . . . . . . . . . . . . . . . 29 7.22.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 30 7.22.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 30 7.23 i 2 c-bus serial interface. . . . . . . . . . . . . . . . . . 30 7.24 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.24.1 typical spi con?gurations . . . . . . . . . . . . . . . 33 7.25 analog comparators . . . . . . . . . . . . . . . . . . . . 34 7.25.1 internal reference voltage. . . . . . . . . . . . . . . . 35 7.25.2 comparator interrupt . . . . . . . . . . . . . . . . . . . 35 7.25.3 comparators and power reduction modes . . . 35 7.26 kbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.27 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 36 7.28 additional features . . . . . . . . . . . . . . . . . . . . . 37 7.28.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . 37 7.28.2 dual data pointers . . . . . . . . . . . . . . . . . . . . . 37 7.29 flash program memory . . . . . . . . . . . . . . . . . 37 7.29.1 general description . . . . . . . . . . . . . . . . . . . . 37 7.29.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.29.3 flash organization . . . . . . . . . . . . . . . . . . . . . 38 7.29.4 using ?ash as data storage . . . . . . . . . . . . . . 38 7.29.5 flash programming and erasing. . . . . . . . . . . 38 7.29.6 icp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.29.7 iap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.29.8 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.29.9 power-on reset code execution . . . . . . . . . . . 39 7.29.10 hardware activation of the bootloader . . . . . . 40 7.30 user con?guration bytes. . . . . . . . . . . . . . . . . 40
nxp semiconductors P89LPC9301/931a1 8-bit microcontroller with accelerated two-clock 80c51 core ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 9 april 2009 document identifier: P89LPC9301_931a1_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 7.31 user sector security bytes . . . . . . . . . . . . . . . 40 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 41 9 static characteristics. . . . . . . . . . . . . . . . . . . . 42 9.1 current characteristics . . . . . . . . . . . . . . . . . . 44 9.2 internal rc/watchdog oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 bod characteristics . . . . . . . . . . . . . . . . . . . . 51 10 dynamic characteristics . . . . . . . . . . . . . . . . . 52 10.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2 isp entry mode. . . . . . . . . . . . . . . . . . . . . . . . 58 11 other characteristics . . . . . . . . . . . . . . . . . . . . 59 11.1 comparator electrical characteristics . . . . . . . 59 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 60 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 62 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 63 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 16 contact information. . . . . . . . . . . . . . . . . . . . . 63 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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